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Guild: wafer.space Community
Channel: 📐 - Designing / 📦-cob / WSBB PCB panel designs post-run1
After: 2026-08-31 11:59 p.m.
Before: 2026-10-01 12:00 a.m.
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[2026-09-04 3:24 p.m.] saladchap
Thought I'd start a thread here - not a fire but we are expecting to want to update the breakout PCB panels for run 2 onwards, based on feedback from the COB supplier(s)

Examples of current suggestions have been for slighlty different rails between panels and different qty of rows and columns. I expect that we can confirm any changes by the end of this month or early October, then be ready to order boards mid October. CC @Andrew Wingate and @RebelMike and @Tim 'mithro' Ansell


[2026-09-04 3:25 p.m.] saladchap
so TLDR: no action for now, but expect a request for some board/panel revs early Oct and hopefully some time for doing the updates in first couple of weeks of Oct


[2026-09-04 3:25 p.m.] saladchap
I'll share further updates here as and when makes sense


[2026-09-04 3:39 p.m.] rebelmike
Note there's this issue on the CoB repo with some potential changes for discussion: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11

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https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11
RUN-2 Change Requests · Issue #11 · wafer-space/chip-on-board-wir...
There are a number of changes we may or may not be making for the run-2 versions. Current List: All boards 4 layers Location of the pin1 fiducial Globtop bubble fixes No vias/holes/etc. under globt...

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[2026-09-04 11:02 p.m.] mithro_
I think this is less about the layout of the CoB board themselves and more about how they are panalized? @stuart - Is that correct?


[2026-09-05 7:45 a.m.] saladchap
Yes that's correct, although I wouldn't rule out small tweaks like soldermask between the die and bond pads, area for serial number and similar


[2026-09-05 7:46 a.m.] saladchap
Afair one of the die boards still has soldermask between the die and pads for example. I'll ensure we get feedback from the new bonding places so we have a spec to work from

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